SSS2302 n-channel enhancement mode mosfet product summary v ds (v) i d (a) 20v 2.4a r ds(on ) ( m ) ma x 60 @v gs = 4.5 v 1 15 @v gs = 2.5 v south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 3.1 ) 1 absolute maximum ra tings (t a = 25 c unless otherwise noted) thermal characteristics parameter symbol limi t uni t o drain-source v oltage gate-source v oltage drain current-continuous @ t c = 25 c -pulse d drain-source diode forward current maximum power dissipatio n operating junction and storage t emperature range thermal resistance, junction-to-ambient o a a a b v ds v gs i d i dm i s p d t j , t stg r ja 20 v v a a a c/ w w c o o 8 2. 4 10 0.95 0.90 -55 to 150 11 5 so t- 23 d g s d g s fe at ures super high dense cell design for low r ds(on ) . rugged and reliable. sot -23 package. pb free.
SSS2302 2 electrical characteristics (t a = 25 c unless otherwise noted) o uni t symbol parameter condition mi n ty p ma x c zero gate v oltage drain current drain-source breakdown vo ltage gate-body leakage gate threshold vo ltage drain-source on-state resistanc e bv dss i dss i gss v gs(th ) r ds(on) v gs =0v , i d =250 a v ds =20v , v gs =0v v gs = 8v , v ds =0v v ds =v gs, i d =50 a v gs =4.5v , i d =3.6a v gs =2.5v , i d =3.1a m v v a na 20 1 100 1. 2 60 11 5 on-state drain current forward tr ansconductanc e tu rn-on delay ti me rise t im e tu rn-of f delay t im e fall ti me i d(on) g fs t d(on) t r t d(off ) t f v ds =5v , v gs =2.5v v ds =5v , i d =3.6a v dd =10 v, v gen =4.5v , r l =2. 8 4 8 55 15 10 7 ns p f s a input capacitanc e output capacitanc e reverse t ransfer capacitance c is s c oss c rss v ds =15v v gs =0v f=1.0mhz 320 105 72 to tal gate charge q g 4 i d =3.6a, r gen =6 , nc v 1. 3 0.76 0.65 1. 5 v gs =0v , i d =1a i d =3.6a, v gs =4.5v v sd q gs q gd diode forward vo ltage gate-source charge gate-drain charge v ds =10 v, notes a. surface mounted on fr4 board, t <10 sec. b. pulse t est pulse width < 300 s, duty cycle < 2% . c. guaranteed by design, not subject to production testing. - - - 10 45 70 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 3.1 )
SSS2302 3 v ds , drain-to-source vo ltage (v ) i d u c n i a r d , ) a ( t n e r r figure 1. output characteristic s 0 1 2 3 4 5 v gs , gate-to-source vo ltage (v ) i d u c n i a r d , ) a ( t n e r r figure 2. thansfer characteristic s 0 0.5 1 1.5 2 2.5 3 25 20 15 10 5 0 - 5 5 c o 25 c o tj = 125 c o r , ) n o ( s d a t s i s e r - n o n c e a m r o n ( d e z i l ? ) -55 -25 0 25 50 75 100 125 2. 2 1. 8 1. 4 1.0 0.6 0.2 0 figure 4. on-resistance va riation with t emperatur e v gs = 4v t j , junction te mpertature ( c ) o v gs = 2.7a v ds , drain-to-source vo ltage (v ) e c n a t i c a p a c , c ( p f ) figure 3. capacitance 0 5 10 15 20 25 3 0 c i s s c o s s c r s s 1000 0 800 600 400 200 r o n , h t v d e z i l a m r u o s - e t a g e r h t e c v d l o h s e g a t l o tj , junction te mperature ( c ) figure 5. gate threshold va riatio n with t emperatur e o -50 -25 0 25 50 75 100 125 v ds = v gs i d = 250 ? a 1. 3 1. 2 1. 1 1. 0 0. 9 0. 8 0. 7 0 v b s s d i l a m r o n , z e d r u o s - n i a r d o d k a e r b e c g a t l o v n w e figure 6. breakdown vo ltage va riatio n with t emperatur e tj , junction te mperature ( c ) o -50 -25 0 25 50 75 100 125 1. 3 1. 2 1. 1 1.0 0.9 0.8 0. 7 i d = 250 ? a v gs = 5v~2.5v v gs = 2v v gs = 1.5v v gs = 0v , 0.5v , 1 v 10 8 6 4 2 0 south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 3.1 )
SSS2302 4 i ds , drain-source current (a ) g , s f n o c s n a r t d u c t a n c e ( ) s 0 5 10 15 20 2 5 figure 7. t ransconductance va riation with drain current v ds = 5v i s d - e c r u o s , r r u c n i a r ) a ( t n e 20. 0 v sd , body diode forward vo ltage (v ) figure 8. body diode forward vo ltage va riation with source current 0.4 0.8 1.2 1.6 2.0 2. 4 v g s c r u o s o t e t a g , g a t l o v e ) v ( e figure 9. gate charge qg , t otal gate charge (nc) 0 1 2 3 4 5 5 4 3 2 1 0 i d u c n i a r d , ) a ( t n e r r 0.01 v sd , drain-to-source vo ltage (v ) figure 10. maximum saf e operating area 0.1 1 10 20 5 0 5 0 1 0 1 0. 1 v gs = 4 v single pulse t c = 25 c o r d s ( o n ) limit 12 1 0 8 6 4 2 0 10. 0 0. 0 t j = 25 c o 1. 0 d c 1 s 1 0 0 m s 1 0 m s v ds = 4.5v i d = 2 a south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 3.1)
SSS2302 5 figure 11 . switching t est circuit v gs r ge n v out v dd v in d r l g s figure 12. switching w aveforms inver ted pulse width t r t d(on ) v out v in t on t of f t d(of f) t f 10% 50% 50% 90% 10% 90% 10% 90% figure 13. normalized thermal t ransient impedance curve t1 t2 p dm 1. r ja(t) = r(t)*r ja 2. r ja = see datasheet 3. t jm - t a = p dm *r ja(t ) 4. duty cycle, d = t1/t2 1 10 -4 10 -3 10 -2 10 -1 10 -5 0.01 1 0. 1 10 r a m r o n , ) t ( f e d e z i l e v i t c e f n e i s n a r t r e h t t d e p m i l a m a n c e duty cycle = 0. 5 square w ave pulse duration (sec) 10 10 2 10 3 0. 2 0. 1 0.0. 5 0.02 0.01 single puls e south sea semiconductor reserves the right to make changes to improve reliability or manufacturability without advance notice. south sea semiconductor , january 2008 (rev 3.1 )
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